1. Field of the Invention
The present invention relates to a multi-layer capacitor, a wiring board, and a high-frequency circuit, and, more particularly, to a multi-layer capacitor useful in a high-frequency circuit, and a wiring board and a high-frequency circuit, both of which include the multi-layer capacitor.
2. Description of the Related Art
The most common multi-layer capacitor conventionally available is constructed of a ceramic dielectric material, for example, and includes a plurality of dielectric layers laminated with an internal electrode interposed therebetween. To construct a plurality of capacitors, a plurality of pairs of first and second internal electrodes are alternately laminated with particular dielectric layers sandwiched therebetween in the direction of lamination. A capacitor body is thus constructed.
First and second external terminal electrodes are respectively disposed on first and second end surfaces of the capacitor body. The first internal electrode has a lead extending to the first end surface of the capacitor body, and the lead is electrically connected to the first external terminal electrode. The second internal electrode has a lead extending to the second end surface, and the lead is electrically connected to the second external terminal electrode.
In the multi-layer capacitor, a current flows from the second external terminal electrode to the first external terminal electrode. More specifically, the current flows from the second external terminal electrode to the second internal electrode, and flows to the first internal electrode via a dielectric layer from the second internal electrode, and finally reaches the first external terminal electrode via the first internal electrode.
The equivalent circuit of the capacitor is a serial connection of C, L, and R, where C represents the capacitance of the capacitor, L represents an equivalent series inductance (ESL), and R represents an equivalent series resistance (ESR) which mainly consists of the resistance of the electrodes.
The equivalent circuit of the capacitor has a resonance frequency of f0=1/{2xcfx80(LC)xc2xd}, and cannot function as a capacitor in a frequency range above the resonance frequency. In other words, the smaller the inductance L, namely, ESL, is, the higher the resonance frequency f0 becomes, and the capacitor accordingly can work on a higher frequency. Although making the internal electrode of copper to reduce ESR has been contemplated, a capacitor having a small ESL is required if it is intended for use in a microwave range.
A low ESL is also required of a capacitor which is used as a decoupling capacitor connected to a power supply circuit which feeds power to a microprocessing unit (MPU) chip for use in a work station or a personal computer.
FIG. 19 is a block diagram showing an example of the configuration of the above-referenced MPU 31 and a power supply 32.
Referring to FIG. 19, MPU 31 includes an MPU chip 33 and a memory 34. The power supply 32 feeds power to the MPU chip 33. A decoupling capacitor 35 is connected along the power line that extends from the power supply 32 to the MPU chip 33. Signal lines extend between the MPU chip 33 and the memory 34.
Like an ordinary decoupling capacitor, the decoupling capacitor 35, associated with MPU 31, is used to absorb noise and smooth fluctuations in power supply voltage. The MPU chip 33 has an operating frequency of 500 MHz or higher, and some chips reaching an operating frequency of 1 GHz are currently under development. In high-speed applications keeping pace with such an MPU chip 33, a quick power supply function is required of the capacitor. The quick power supply function feeds power from electricity stored in a capacitor within several nanoseconds when power is instantaneously needed, such as at startup.
The MPU 31 thus needs a decoupling capacitor 35 having an inductance as low as possible, for example, 10 pH or lower inductance. Thus, a capacitor having a low inductance is needed for functioning as the decoupling capacitor.
For instance, an MPU chip 33 having an operating clock frequency of 450 MHz is now supplied with 1.8 volts to 2.0 volts DC, and its power consumption is 23 W, i.e., with a current of 12 A being drawn. To reduce the power consumption, the MPU 31 is set to operate in a sleep mode at a power consumption of 1 W when not in use. When the MPU 31 is changed from sleep mode to an active mode, the MPU chip 33 needs to be supplied with power enough for the active mode to start within several clocks. At the operating clock frequency of 450 MHz, power must be supplied within 4 to 7 nanoseconds when the MPU 31 is changed from the sleep mode to the active mode.
Since the power feeding from the power supply 32 is not fast enough, the charge stored in the decoupling capacitor 35 in the vicinity of the MPU chip 33 is first discharged to feed power to the MPU chip 33 until the power feeding from the power supply 32 starts.
At an operating clock frequency of 1 GHz, the ESL value of the decoupling capacitor 35 in the vicinity of the MPU chip 33 needs to be 10 pH or smaller for the decoupling capacitor 35 to function in the manner described above.
The ESL of typical multi-layer capacitors ranges from 500 pH to 800 pH, which is far from the above-referenced value 10 pH. Such an inductance component is created in the multi-layer capacitor because a magnetic flux, the direction of which is determined by a current flowing through the multi-layer capacitor, is created, and a self inductance is created due to the magnetic flux.
Under these situations, the structures of multi-layer capacitors that can achieve a low ESL have been proposed in U.S. Pat. No. 5,880,925, Japanese Unexamined Patent Publication No. 2-159008, Japanese Unexamined Patent Publication No. 11-144996, and Japanese Unexamined Patent Publication No. 7-201651.
The above disclosed method of achieving a low ESL is primarily based on the cancellation of magnetic fluxes induced in the multi-layer capacitor. To cancel magnetic fluxes, the direction of a current flowing in the multi-layer is diversified. To diversify the direction of the current, the number of terminal electrodes disposed on the external surface of the capacitor body is increased so that the number of leads of internal electrodes electrically connected to the respective external terminal electrodes is increased. At the same time, the leads of the internal electrodes are aligned in several different directions.
The effectiveness of the proposed method of achieving a low ESL in the multi-layer capacitor is not sufficient.
For example, U.S. Pat. No. 5,880,925 and Japanese Unexamined Patent Publication No. 2-159008 disclose a structure in which the leads of internal electrodes extend to opposing sides of a capacitor body. It is estimated that such a structure achieves a low ESL of about 100 pH.
Japanese Unexamined Patent Publication No. 11-144996 discloses a structure in which the leads of internal electrodes extend to four sides of a capacitor-body, and describes that the best ESL value is 40 pH.
Japanese Unexamined Patent Publication No. 7-201651 discloses a structure in which the leads of the internal electrodes extend to the top and bottom major surfaces of a capacitor body, and describes that the best ESL value is 50 pH.
For this reason, a plurality of multi-layer capacitors connected in parallel must be conventionally mounted on a wiring board to achieve an ESL value as low as 10 pH in a high-frequency circuit having a multi-layer capacitor for an MPU chip (including a power supply line). As a result, the mounting area required for the plurality of multi-layer capacitors increases, which prevents achievement of a compact design of an electronic device included in a high-frequency circuit.
To overcome the problems described above, preferred embodiments of the present invention provide an improved multi-layer capacitor which achieves a very low ESL value and provide a wiring board and a high-frequency circuit, both of which incorporate the multi-layer capacitor which achieves very low ESL.
A multi-layer capacitor of a preferred embodiment of the present invention includes a capacitor body having two opposing major surfaces and four side surfaces joining the two opposing major surfaces. The capacitor body includes a plurality of dielectric layers extending parallel to the major surfaces and at least one pair of first and second internal electrodes which are opposed to each other with a particular dielectric layer interposed therebetween to define a capacitor unit.
The multi-layer capacitor of the present invention is constructed to overcome the problems with conventional devices. More specifically, a first side-surface terminal electrode and a second side-surface terminal electrode are provided on at least one of the side surfaces of the capacitor body, while at least one major-surface terminal electrode is provided on at least one of the major surfaces of the capacitor body.
The first side-surface terminal and the second side-surface terminal are respectively electrically connected to the first internal electrode and the second internal electrode, while one of the first internal electrode and the second internal electrode is electrically connected to the major-surface terminal electrode through a via hole conductor penetrating the dielectric layer.
The first side-surface terminal electrode and the second side-surface terminal electrode are preferably provided on each of two side surfaces, and are more preferably provided on each of the four side surfaces.
The first side-surface terminal electrode and the second side-surface terminal electrode are preferably arranged adjacent to each other on each of the side surfaces, and are more preferably arranged adjacent to each other along each of the four side surfaces.
The major-surface terminal electrode may be provided on one of the two major surfaces or may be provided on each of the two major surfaces.
The via hole conductor may include a portion which penetrates the internal electrode in a manner such that the via hole conductor remains electrically isolated from the internal electrode which is not connected thereto, This arrangement is implemented when a plurality of internal electrodes, i.e., the first and second internal electrodes, are included.
The major-surface terminal electrodes preferably include a first major-surface terminal electrode and a second major-surface terminal electrode, which are respectively electrically connected to the first internal electrode and the second internal electrode. In this case, the first major-surface terminal electrode and the second major-surface terminal electrode may be provided on only one of the two major-surfaces or may be provided on each of the two major surfaces. In each of the major surfaces, the one arranged closest to the first major-surface terminal electrode is preferably the second major-surface terminal electrode and the one arranged closest to the second major-surface terminal electrode is preferably the first major-surface terminal electrode.
When the first and second major-surface terminal electrodes are arranged, the first major-surface terminal electrode may be provided on one major surface while the second major-surface terminal electrode may be provided on the other major surface.
Preferably, the via hole conductors include a first via hole conductor which electrically connects the first internal electrode to the first major-surface terminal electrode such that the first via hole remains electrically isolated from the second internal electrode, and a second via hole conductor which electrically connects the second internal electrode to the second major-surface terminal electrode such that the second via hole remains electrically isolated from the first internal electrode.
The side-surface terminal electrodes may include an electrode which straddles two adjacent side surfaces.
Preferably, the major surface of the capacitor body of preferred embodiments of the present invention is generally square.
The multi-layer capacitor of preferred embodiments of the present invention is useful as a decoupling capacitor connected to an electrical circuit of a microprocessing unit chip in a microprocessing unit.
In addition, a multi-layer capacitor according to preferred embodiments of the present invention may be included in and mounted on a wiring board. A microprocessing unit chip may be mounted on a wiring board of this preferred embodiment of the present invention.
Preferably, the major-surface terminal electrode on the multi-layer capacitor is connected to the wiring board using a bump connecting electrode. The side-surface terminal electrode of the multi-layer capacitor may be connected to the wiring board.
Further, another preferred embodiment of the present invention may be a high-frequency circuit incorporating the multi-layer capacitor of various preferred embodiments of the present invention.
Other features, elements, characteristics and advantages of the present invention will be described in detail below with reference to the attached drawings.